1. Technical Field
The present invention relates to a process for manufacturing a TFT (Thin Film Transistor) device realized with source and drain regions having gradual dopant profile and corresponding device.
The invention particularly, but not exclusively, relates to a TFT device of the non-self-aligned type and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, in the last years polycrystalline silicon Thin Film Transistors (TFTs) have raised a great interest for their applications in large area microelectronics (LAM). They have taken an important role thanks to the possibility of combining a low realization cost with high performances. In fact, these TFT transistors show neatly higher performances with respect to the transistors realized with amorphous silicon in terms of mobility and stability.
Moreover, the introduction of a re-crystallization step through exposure to excimer laser (ELC, i.e., Excimer Laser Crystallization) in the manufacturing processes of these devices has allowed in fact to considerably improve the quality of the polysilicon layer they are made of, both increasing the grains sizes and reducing the density of the defects at the edges and inside the grains themselves. The combination of more extended grains and low density of defects allows to realize TFT transistors with high mobility and field effect (μfe) suitable for realizing AMLCD, i.e., Active Matrix Liquid Crystal Displays or AMOLED, i.e., Active Matrix Organic Light Emitting Displays) to be used in laptops and in latest generation cell phones (UMTS), using the TFT transistors not only as switches of the active matrix but also for realizing the integrated elements of the addressing and control circuitry for the rows and the columns of the matrix itself.
A first known process for realizing TFT comprising source-drain regions self-aligned to the gate electrode provides the formation on a glass substrate of an amorphous silicon layer, which is followed by a crystallization step through laser for transforming the amorphous silicon layer into a polycrystalline silicon layer. On this latter layer the gate dielectric is deposited, and then the gate electrode is formed, which serves as mask for the successive dopant ionic implantation step which realizes the source-drain regions inside the polysilicon layer.
The process then requires a further annealing passage (either laser or thermal) for the removal of the defects induced by the implantation step and the dopant activation.
Since these devices are realized on glass substrates, the implantation step is not followed by a conventional diffusion step of the dopant atoms for realizing source-drain regions diffused towards the device channel (under the gate electrode) and thus these source-drain regions have a very high concentration gradient (“abrupt” junction type) originating high electric fields during the operation of the TFT device. In fact, the diffusion step of the dopant atoms implies a thermal step at high temperature which would deteriorate the glass substrate.
Although advantageous under several aspects, these TFT transistors which are formed with known “abrupt” junctions show problems linked to the high biasing voltages of the “drain” region which reduce the electric performances of the TFT transistors, such as for example the anomalous increase of the output current, also called “kink” effect, besides the degradation of the electric characteristic linked to the presence of hot carriers and to an increase of the turn-off current of the TFT transistor known as “leakage” current.
In fact, the electric field associated with the biasing voltage of the “drain” region is in turn sensitive to the dopant profile of the “drain” region next to the channel region, in particular when the dopant profile of the “drain” region, next to the channel region, has a very high concentration gradient (“abrupt” junction type).
Therefore this first known process leads to the formation of source and drain regions with high concentration gradient dopant profile and, as per what has been mentioned above, under biasing conditions of the “drain” region, imply an increase of the electric field in the channel regions with subsequent electric deterioration of the TFT transistor performances.
A second known process for realizing TFT comprising source-drain regions non-self-aligned to the gate electrode provides the formation on a glass substrate of an amorphous silicon layer which is followed by a dopant ionic implantation step for realizing the source-drain regions inside the amorphous silicon layer. A crystallization step through laser is then carried out, which activates the implanted dopant and further causes the diffusion of the dopant atoms towards the channel region comprised between the source/drain regions, with a diffusion length which depends on the number of laser pulses applied.
Due to the photolithographic tolerances, the overlapping between the gate electrode and the source-drain regions cannot be lower than about 2 μm, resulting in parasitic capacitances.
It is also known that the source/drain regions of the non-self-aligned TFT can be realized with doped silicon layers deposited through PECVD on an amorphous silicon layer, as described in the article “Thin Film Transistors Fabricated by In Situ Doped Unhydrogenated Polysilicon Films Obtained by Solid Phase Crystallization” by L Pichon, K Mourgues, F Raoult, T Mohammed-Brahim, K Kis-Sion, D Briand and O Bonnaud published on Semicond. Sci. Technol. 16 (2001) 918-924.
In this latter process, the doped layer on the channel is removed prior to the silicon crystallization step. This removal step is realized through a plasma etching of CF4+O2 (RIE) which realizes regions with vertical side walls as shown in FIG. 4. This removal process is not selective between the doped silicon layer and the underlying amorphous silicon layer, thus the etching time should be exactly calculated. Moreover, the plasma used for the etching can generate defects in the etched region, which is the active portion of the channel.
A further process for the manufacturing of the TFT transistors with gradual junctions, called lift-off, is described in the article “A Novel Fabrication Process For Polysilicon Thin film Transistors With Source/Drain Contacts Formed by Deposition and Lift-Off Of Heavily Doped Layers” by G. Fortunato et al, published on “Solid State Electronics”, vol. 46 (2002) 1351-1358, and shown with reference to FIGS. 1A-1O.
In particular, on a glass substrate 1a silicon nitride layer 2, a first silicon oxide layer 3, an hydrogenated amorphous silicon layer 4 (a-Si:H), a second silicon layer 5 and a photo-lithographic mask 6 provided with first openings 7 of a first width are formed in cascade.
As shown in FIG. 1C, the second oxide layer 5 is selectively removed through the first openings 7 to form second openings 8, in this second oxide layer 5, of greater width than the first openings 7.
A first strongly doped polysilicon layer 9 is then formed on the photo-lithographic mask 6 and a second strongly doped polysilicon layer 11 on the hydrogenated amorphous silicon layer 4 inside the second openings 8.
In particular, the second polysilicon layer 11 is not in direct contact with the walls of the second openings 8 and forms the source and drain regions of the TFT transistor 10, which will be hereafter indicated with the same reference number 11. As shown in FIG. 1D, a gap region is then formed between the second oxide layer 5 and the source/drain regions 11.
The process then goes on with the removal of the photo-lithographic mask 6 and of the first polysilicon layer 9 (lift-off) as shown in FIG. 1E.
Also the second oxide layer 5 is then removed, as shown in FIG. 1F.
The presence of the gap region facilitates the removal step of the second oxide layer 5.
As shown in FIG. 1G, the process goes on with a de-hydrogenation step which is followed by a re-crystallization step through exposure to an excimer laser beam (ELC, i.e., Excimer Laser Crystallization).
At the end of this step the hydrogenated amorphous silicon layer 4 has been transformed into a polycrystalline silicon layer 4a wherein the source/drain regions 11 are integrated as shown in FIG. 1H.
A second photolithographic step is then carried out for removing the silicon layer which is outside the source/drain regions 11 and the device channel so as to delimit the active area of the TFT transistor 10. A third oxide layer 13 is then formed on the whole exposed surface, as shown in FIG. 11.
By means of a third photolithographic step which makes use of a further photolithographic mask 14 provided with third openings 15 aligned to the source/drain regions 11, the third oxide layer 13 is removed until the polysilicon layer 4a is exposed, for opening contact vias 16, as shown in FIG. 1L.
Once a metallic layer 17 is formed on the whole device, as shown in FIG. 1M by means of a fourth photolithographic step which makes use of a further photolithographic mask provided with fourth openings 19 aligned to the third openings 15 with smaller width, the metallic layer 17 is removed through the fourth openings 19, to form the contacts CT of the TFT transistor 10, as shown in FIGS. 1N and 1O.
This lift-off process of the source/drain regions 11 could be realized without needing the presence of the second oxide layer 5, however, the lift-off step of the source/drain regions 11 from the resist mask 6 does not ensure a neat definition between the active regions and the regions to be removed after the lift-off process itself. The process therefore shows a certain criticality and to overcome this problem the second silicon oxide layer 5 has been exactly introduced immediately below the resist mask 6. In this way in fact, by subjecting the second oxide layer 5 to a selective and prolonged etching, shown in FIG. 1C, it is possible to succeed in removing it far below the edge of the resist mask 6 thus creating a discontinuity that makes the lift-off process easier.
However, although this measure removes the criticality of the feasibility of the source/drain regions 11 due to the removal of the oxide layer 5 which has the function of hardmask after the lift-off process has occurred, it introduces another one which, even if not critical from a feasibility viewpoint, is instead critical from an industrial viewpoint since it is linked to the reproducibility of the openings 8.
In fact, the etching step of the oxide layer 5, after the photolithographic step, necessarily occurs though wet process and below the resist mask 6. The control of the lateral width of the openings 8 is critical and thus the width and the lateral profile of the source/drain regions 11 are not repeatable.
In fact, the lateral profile of the polysilicon layer 11 which is grown inside the openings 8 strictly depends on the width of the openings 8 below the mask 6 that, as already said, is not controllable and repeatable.
The poor controllability on the oxide layer 5 which is laterally etched, besides on the variation of the channel length, has then negative effect also on the shape of the dopant profile of the source/drain regions after the crystallization step.
In fact, this crystallization step, necessary for activating and diffusing the dopant of the polysilicon layer 11 in the polysilicon layer 4a, provides again in the polysilicon layer 4a a similar dopant profile which preserves the memory of the previous process originating source and drain regions 11 with dopant profile also being not enough repetitive from an industrial point of view, more or less of the “abrupt” type, depending on how the process tolerances associated with the photolithographic step are combined with the photolithographic step, etching step as well as with the greater or minor selectivity of the lift-off process in general associated with the resist/residual deposited material removal and residual oxide removal steps and this causes electric performances of the device with wide excursion of the control parameters.
Therefore, the lift-off process implies an intrinsic poor reproducibility of the structure of the active region of the transistor 10 which in turn implies a wide dispersion of the electric parameters, to the disadvantage of a low product performance which make the process little attractive on an industrial scale.